This invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to a multiple resonant frequency decoupling capacitor which has an increased bandwidth.
It is well known in the field of micro-electronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. Generally, the prevention of coupling of undesired high frequency noise or interference into the power supply for the integrated circuit is accomplished by connecting a decoupling capacitor between the power and ground leads of the integrated circuit (IC).
One connection scheme which has been found to be quite successful is to mount a decoupling capacitor under the integrated circuit. Such decoupling capacitors are commonly available from Rogers Corporation, (assignee of the present application) and sold under the trademark MICRO Q. Examples of these decoupling capacitors are found in U.S. Pat. Nos. 4,475,143; 4,502,101 and 4,748,537 all of which are assigned to the assignee hereof.
U.S. Pat. Nos. 4,626,958; 4,667,267; 4,658,327; 4,734,818; 4,734,819 and 4,853,826 are also assigned to the assignee hereof and incorporated herein by reference. These patents disclose decoupling capacitors which are particularly well suited for pin grid array and plastic lead chip carrier packages. For example, the PGA decoupling capacitor of U.S. Pat. No. 4,853,826 comprises a dielectric material sandwiched between a pair of conductors. A plurality of flat plates or skirts are provided along a periphery of each conductor. These skirts extend outwardly a short distance generally in the plane of the metal conductors to which they are attached and are then bent downwardly so as to extend in the direction which is perpendicular to the planes of the conductors. The entire assembly, with the exception of the plural traversaly extending skirt portions, may then be encapsulated with a suitable non-conductive material.
This flat coupling capacitor adapted for mounting directly under a pin grid array package results in a lower decoupling loop, thus providing a more effective decoupling scheme. The capacitor of U.S. Pat. No. 4,853,826 also contributes to a saving of board space, i.e., takes up less "real estate" on the printed circuit board, by resting entirely under the PGA package.
With integrated circuits having a high number of gates per unit area of Silicon or Gallium Arsenide and having high clock rates with small signal rise times an improved decoupling schemes is required. With the higher clock frequencies the existing decoupling capacitors have not been effective in suppressing the noise coupled into the power leads. The above-identified capacitors have attempted to minimize the decoupling loop inductance which is what ultimately limits the highest frequencies effectively decoupled by the capacitor. However, the highest noise frequency that is decoupled by the present capacitors is not the only source of noise coupled into the power leads from the IC. The prior art capacitors only filter out the highest frequency due to self inductance of the capacitor and most importantly the fact that they are elements having only one resonant frequency.
While the prior art capacitors are well suited for their intended purpose a need exists to prevent coupling of noise from the other frequencies.